1. Technical Field
The present disclosure relates to integrated circuits having a processing unit and a memory space and, more particularly, to one or more memories addressable by the processing unit and to a method of configuring the same.
2. Description of the Related Art
In particular, the present disclosure relates to Radio-Frequency Identification (RFID) tags. Such tags generally include send and receive circuits for sending and receiving modulated radioelectric signals to exchange data with a reader, an electric power supply circuit to generate a supply voltage of the integrated circuit using radioelectric signals received, a processing unit, and a memory space having a non-volatile memory, of the EEPROM type for example.
In certain applications, the memory space of such a tag is divided into memory banks, each reserved for specific functions. Each of the memory banks is associated with an access number to be used to access a data location in the memory bank in combination with a logic address of the location in the memory bank.
When a certain level of security is required, the memory banks can be individually read- or write-locked, made inaccessible. This arrangement enables various people to intervene separately in the process of manufacturing, customizing, adapting to a specific application and using the chip, while providing protection against fraudulent operations.
The mode for addressing the memory space by memory banks involves a specific address decoding to convert a logic address associated with a memory bank number into a physical address capable of being processed by the memory. Indeed, such a decoding depends both on the number of memory banks, on the position, and on the size of each one of them. Now, for reasons relating to cost saving and speed of execution, the address decoding is generally performed by hard-wired logic. The result is that the configuration of the memory space of a tag is generally set.